The present invention relates generally to a semiconductor device, and more particularly to a method of forming a gate of a semiconductor device, the gate having a dummy gate pattern that protects a gate pattern, a method of forming a metal line that supplies the power for a semiconductor device and transfers a signal, and a semiconductor device including a quad coupled receiver type input/output buffer.
In general, a typical semiconductor device includes devices such as transistors, capacitors, and resistors, and is formed with wirings that electrically connect the devices to one another.
When designing a semiconductor device, the electrical properties, the process influence, and the structural liability of the devices and the wirings should be ensured. More particularly, as a semiconductor device becomes highly integrated, the importance of the pattern and the layout of both the device and the wiring tends to increase.
Further, it is important to consider the gate pattern of MOS transistors when designing the device. The gate of the MOS transistor includes a gate line and a gate pad that are integrally connected to each other. Herein, the gate pad is a portion laid out so that a gate line and a metal layer overlap, and the gate line and the metal layer are electrically connected via a gate contact. Typical the gate pad has a rectangular shape and takes an overlap margin into consideration.
FIG. 1A is an example of a typical gate pad in a MOS transistor of a general semiconductor device. A gate line GL is formed over an active region 10, which constitutes a MOS transistor region, and a gate pad 12 is formed at the end of the gate line GL. Contacts BLC1 that constitute a source and a drain are formed over the active region at both sides of the gate line GL, and contacts BLC2, which are electrically connected to a metal line (not shown) at an upper portion thereof, are formed over the gate pad 12.
Herein, the gate pad 12 is laid out such that a side thereof adjoins an extended end of the gate line GL with a step.
FIGS. 1B and 1C illustrate a MOS transistor formed with at least two gates over the same active region 10. The gate lines GL have different lengths and each gate pad 12 is laid out such that a side thereof adjoins an extended end part of the gate line GL with a step. Also, each gate pad 12 is laid out in the same direction as the gate line GL to which the gate pad 12 adjoins.
The gate pattern in FIGS. 1A through 1C has an advantage in that the layout area is reduced as wiring connections between MOS transistors are minimized in a layout structure as shown in FIG. 2.
FIG. 2 illustrates a case where MOS transistors are used to construct a single circuit. Herein, a semiconductor device may have a structure that utilizes the same type of MOS transistor and arranges the MOS transistor in a line in one well region 22 defined by an active guard 20.
Each gate pad 12 is connected to the corresponding gate line GL by adjoining the gate pad 12 to the corresponding gate line GL (as in MOS transistor TR1) or by disposing the gate pad 12 at an area outside of an adjacent transistor's active region 10 and extending a portion of the side thereof (as in transistor TR2). Also, each active region 10 is irregularly disposed in the well region 22 according to the connection relationship between the MOS transistors (such as the transistors TR1 and TR2).
When the transistors TR1 and TR2 are disposed as in FIG. 2, the length of connection wiring can be minimized when connected to a drain (or a source) region of the transistor TR1 and a gate of the transistor TR2.
However, in the case of FIGS. 1A through 1C and 2, the gate of each transistor has many critical points, i.e. right-angled corners at portions where the gate line and the gate pad are connected. The critical points can cause a reduction in the process margin and an increase in the resistance due to the layout. Thus, the circuit properties of the transistor are lowered.
Additionally, if the active regions 10 are disposed irregularly (as shown in FIG. 2) in order to minimize the wiring connection between the transistors, the distances ‘GT1’-‘GT4’ between the gate pad region 12 of each transistor and the active guard 20 are different, and the distances ‘AT1’-‘AT2’ between the active region 10 of each transistor and the active guard 20 are different.
Additionally, spaces ‘a’, ‘b’, and ‘c’ between the gates of the adjacent transistors are different. Therefore, the line width of the gate of the transistor may vary as a difference of mass of the gate. Such a variation in the line width of the gate may cause changes in the electrical characteristics of the transistor, and a problem is caused in that it is difficult to operate an optical proximity correction for ensuring a uniform variation in the line width.
Meanwhile, when designing the wiring that includes the gate, it is important to ensure physical and electrical stabilities.
Referring to FIG. 3, in a general semiconductor device, a plurality of block cells BC1 through BC4, which are formed by a gathering of unit cells UC in a peripheral region, is disposed. Power metal line patterns 1 for supplying a power voltage VDD and a ground voltage VSS to each block cell BC1 through BC4 are disposed in parallel to each other, and signal metal line patterns 2 for transferring a routing signal between the block cells are irregularly disposed.
In a process of forming the aforementioned power metal line patterns 1 or signal metal line patterns 2, a chemical mechanical polishing process for formation of an oxide layer and planarization is performed after the formation of the metal line patterns 1 and 2.
However, as shown in FIG. 3, when the spaces between the metal line patterns 1 or 2 are different from one another, a dishing phenomenon can occur in a region having a low pattern density due to a planarization process used to etch metal. Therefore, a problem exists, in that it is difficult to ensure the stability of the metal line pattern when the metal line patterns are laid out as shown FIG. 3.
In order to ensure the stability of the metal line pattern, dummy metal line patterns 3 may be disposed between the metal line patterns 1 and 2 as shown in FIG. 4, which corresponds to FIG. 3.
In the case of FIG. 4, the dummy metal line patterns 3 disposed between the metal line patterns 1 and 2 are formed in a bar type parallel to the longitudinal direction of the metal line patterns 1 and 2. Also, dummy metal line patterns 3 have a predetermined width W defined as a design rule and a length L corresponding to a length of adjacent metal line pattern 1 or 2.
However, in the case of FIG. 4, a defect can occur when a particle P forms a bridge between the metal line pattern 1 or 2 and the dummy metal line pattern 3.
Meanwhile, when designing the wiring, it is also important to consider the electrical characteristics of the MOS transistor.
An input/output buffer of a semiconductor device having the MOS transistor should be designed so as to have a strengthened noise characteristic for a fast response characteristic. Also, the power line used in the input/output buffer should be designed so that the power line is not influenced by noise.
In a semiconductor device operating at a high speed, a quad coupled receiver type input/output buffer having a differential amplification structure that compares and amplifies a reference voltage VREF and an input signal IN as shown in FIG. 5 is mainly used.
In the quad coupled receiver type input/output buffer having the differential amplification structure, the electrical characteristics of the two MOS transistors <M11, M21>, <M12, M22>, <M31, M41> and <M32, M42> that form a differential pair or a current mirror should be the same for normal differential amplification.
However, the circuit construction causes the channel lengths of the MOS transistors to be different from one another, and as such the electrical characteristics of each MOS transistor may be different from the expected characteristics when the MOS transistors having different channel lengths are disposed adjacently as shown in FIG. 6.
Specifically, the MOS transistor pair M12 and M22 and the MOS transistor pair M32 and M42 are aligned in a sequence of ‘M12, M32, M22, M42’ as shown in FIG. 6. MOS transistors TR1 and TR2 are disposed at a side of the MOS transistor M12 and at a side of the MOS transistor M42 respectively.
The patterns between the active regions of the MOS transistors are gate dummies GD. The MOS transistors TR1 and TR2 of FIG. 6 correspond to the MOS transistors M5, INV1, and INV2, which do not require the same electrical characteristics, in the input/output buffer of FIG. 5.
As shown in FIG. 6, the MOS transistor pair M12 and M22 and the MOS transistor pair M32 and M42 having different channel lengths are alternately disposed. The gate dummy GD is disposed between the MOS transistors in order to minimize a variation in the gate critical dimension of the gate G.
However, since MOS transistors TR1 and M32 having different channel widths are disposed on both sides of a MOS transistor (for example, M12), the gate critical dimension of the gate of the MOS transistor M12 varies even though the gate dummy GD is disposed between the active regions.
In other words, when the channel widths of the adjacent MOS transistors are the same, the MOS transistors can have the electrical characteristics intended by the designer, since the pattern of the gate G of the MOS transistor is not changed as shown in FIG. 7A (distances A1 through A3 between a side surface of the gate and a contact are all the same).
However, when the channel widths of the adjacent MOS transistors are different, the MOS transistors may have electrical characteristics different from those intended by the designer, since the pattern of the gate G of the MOS transistor is changed as shown in FIG. 7B (distances B1 through B3 between a side surface of the gate and a contact are different).